The relentless pursuit of ever shrinking semiconductor devices continues to challenge the limitations of conventional semiconductor materials and fabrication techniques. Conventional semiconductor devices typically comprise a plurality of active devices in or on a common semiconductor substrate. The various transistors are designed for different operating voltages. Conventional practices, therefore, seek to provide transistors having different gate oxide thicknesses depending upon the performance of a particular transistor. Such different performance characteristics typically involve different operating voltages and, consequently, different gate oxide thickness. Typically, transistors operating at a high voltage require a relatively thick gate oxide layer; whereas, transistors designed for relatively lower operating voltages require a relatively thinner gate oxide layer.
Conventional methodology for fabricating semiconductor devices with transistors having different gate oxide thicknesses results in relatively poor quality thin gate oxide layers having defects. These defects cannot usually be removed by annealing and, hence, generate reliability problems, such as gate leakage or gate oxide breakdown. Such conventional methodology employed to fabricate transistors having different gate oxide thicknesses typically involves an excessive number of processing steps, adversely impacts impurity doping profiles with an attendant impact on operating voltage, requires modification of assembly line equipment and adversely impacts the critical gate oxide, i.e., the thin gate oxide for standard CMOS processes or the tunnel oxide for EEPROM processes. Such conventional practices include formation of a thin silicon nitride layer, nitrogen implantation and plasma exposure.
Accordingly, there exists a need for efficient methodology enabling the fabrication of semiconductor devices containing transistors having multiple gate oxide thicknesses with a low thermal budget, minimized dopant diffusion, negligible shift in the electrical parameters of existing transistors, wide flexibility as to the gate oxide thickness and without the need for specialized equipment or techniques, such as nitrogen implantation or plasma processes. There exists a particular need for such methodology enabling the fabrication of semiconductor devices containing various transistors with gate oxides having a thickness accurately tailored to different operating voltages.